Memory controller enhancements

Since pioneering the 256-bit memory interface with their RADEON 9700 PRO VPU, ATI has only made a few enhancements to their memory subsystem. Obviously the most dramatic differences are the increased clock speeds ATI boasts on their high-end boards, and the new memory types supported, particularly GDDR3. This has all changed for RADEON X1800.

One of the most important changes ATI has implemented is by increasing the number of memory controllers present in RADEON X1800. Whereas previous ATI products featured four 64-bit memory controllers, for RADEON X1800, ATI has doubled the number of memory controllers to eight, each 32-bits wide. With more controllers onboard, the X1800 can serve more read/write requests simultaneously and thus increasing efficiency.


In addition to reworking the memory controller configuration, ATI also switched to a ring bus architecture. According to ATI, this new design was necessary to allow the Radeon X1800 to hit much higher memory clocks more efficiently than previous designs.

The ring bus consists of two 256-bit rings and four ring stops, one for each pair of memory controllers. To simplify the routing of the wires and to provide a cleaner signal at high clocks, ATI routes the ring bus around the outer edge of the chip. Data then travels between ring stops until it reaches its destination. The two rings run in opposite directions to ensure that this happens as quickly as possible.


ATI has also moved from a direct-mapped cache to a fully associative cache for its texture, color, and depth/stencil buffer caches along with integrating new arbitration logic that’s more efficient at managing the read/write requests that are sent to the memory controllers. Finally, ATI has implemented better hidden surface removal techniques and better compression into the X1800. For instance, ATI claims that their implementation of hierarchical Z in the RADEON X1800 can catch up to 50% more hidden pixels than previous ATI architectures thanks to a more accurate visibility checking algorithm.