What's so special?

The Current Pentium 3

Let's go over some of the main features of the Katmai design before we compare it to the Coppermine. As we mentioned before, the Katmai Pentium III processor is based on the 0.25 manufacturing process. The current Pentium III processor is based on the P6 core, has 32K of L1 cache, and 512Kb of discrete L2 cache(Burst pipelined synchronous static RAM (BSRAM) w/TagRAM). Note that the L2 cache runs at half the processor clock speed and is separate from the processor core. Current Pentium III processors are only available in the Slot-1 format.

Most current Pentium III processors run on the 100MHz front side bus(FSB), but Intel has recently released two new 0.25 Pentium III processors that operate on the 133MHz FSB. The new 533B and 600B processors use the "B" designation to identify the processor as a 133Mhz FSB model.

The Pentium III also features SSE (Streaming SIMD Extensions), 71 new instructions that greatly increase the efficiency of floating point operations. We've already seen the benefits of SSE in the NVIDIA Detonator drivers in Quake 3. In Quake 3, Pentium III processors get 5-10% more frames per second than Celeron processors of the same speed.

The Coppermine

The Coppermine is very similar to current Pentium III processors. Intel Senior VP, Albert Yu, General Manager of the Microprocessor Products Group has even stated that the Coppermine is basically a Katmai processor on 0.18 technology with integrated L2 cache. The new Coppermine processor will have 256Kb of L2 cache integrated on the chip running at full processor speed. Basically, L2 cache size has been halved, but the speed has been doubled. Coppermine processors will mainly operate on the 133MHz bus, but we will see a couple 100MHz FSB transition processors as Intel shifts all Pentium III to the 0.18 process. Intel will use "E" to identify Coppermine processors. P3-600EB Coppermine processors running on the 133MHz bus have an "EB" to indicate Coppermine and 133Mhz FSB. A P3-500E processor would be a Coppermine chip running on the 100MHz bus.

The Coppermine will also feature PIII SSE, and introduce a new package format, FCPGA. The Flip Chip Pin Grid Array package format was made possible by moving the L2 cache onto the processor core. You may remember that Intel was able to move the Celeron processor to the PPGA (Plastic Pin Grid Array) package for the same reason. Coppermine processors will first be available in SECC2 format (Slot-1), but will switch to FCPGA. The move to FCPGA will allow Intel to shave about $20 off the cost to produce each processor.

The Coppermine FCPGA format uses the same pin layout as current socket370 Celeron processors. Celerons may be able to work in FCPGA sockets, but Coppermine processors won't work with normal socket370 motherboards.