The G4's Features
Nothing RISCed, nothing gained…
As you probably know, the PowerPC architecture is based of the idea of Reduced Instruction Set Computing (RISC). The idea behind RISC is that a processor with a smaller set of possible instructions that are unified in size and format will be able to execute those instructions faster. The Intel x86 architecture allows for instructions between one and 87 bytes in size. In contrast, all PowerPC instructions are 32 bits, no exceptions. This uniformity makes life a lot easier for the engineers designing a processor, and gives them the breathing space necessary to implement tricks that speed up execution. While Intel processors are externally considered CISC, internally, they decode the complicated CISC instructions into easier-to-handle RISC instructions before execution.
One of the features that are easy to implement on a RISC processor is the instruction pipeline. There are always multiple steps to executing a single instruction, whether it is RISC or CISC, integer, floating point, or SIMD. While the actual steps vary from architecture to architecture, the four steps in the major pipeline of the G4 are the fetch, decode/dispatch, execute, and complete/write back stages. Usually it takes a minimum of one processor cycle to complete each step. Older processors were only able to execute one stage at a time, giving them a maximum execution speed of .25 instructions per cycle.
Considering that each stage needs a different set of hardware, the parallel execution of different stages on different instructions is a logical step in processor design. The hardware that makes this possible is called the pipeline. You can see the four pipeline stages of the G4 in the diagram below (taken from the MPC7400 Technical Summary).
The G4 Pipeline