Processor Pathways

In depth

Here is a basic rundown of what is done during each step:

• Fetch: In this stage, the processor grabs the next instruction from the memory subsystem. The instruction may come from the cache or from main memory; the Memory Management Unit handles those details. Up to four instructions can be fetched in one cycle (128-bits).

• Decode/Dispatch: This unit of the processor takes the fetched instruction, decides what class it belongs to (integer, floating point, AltiVec, branch, register, or memory load/store.) It then dispatches (sends) the instruction to the execution unit responsible for that type. A maximum of three instructions can be dispatched per cycle: two can be sent downward on the chart and one sideways to the Branch Processing Unit.

• Execute: This stage of the pipeline does the real work. Like all modern processors, the G4 is superscalar, meaning it has multiple execution units. During one cycle, every one of those 8 units could be executing a different instruction. As you can see, some of the execution units take more cycles than others. A floating-point (FPU) calculation takes three cycles, while each integer unit (IU) only needs one cycle. The VPU and the VALU are the Vector Permutate Unit and the Vector Arithmetic Logic Unit that comprise the "Velocity Engine". When any execution unit is finished, it sends its results to the Write-Back stage.

• Completion/Write-Back: This stage of the pipeline puts the instructions back in their original order, writes the result of the calculation to the result register, and takes care of any conflicts that may have arisen.

  For those interested in the intricate workings of the 7400 CPU, here is a slightly more detailed schematic of its functional units.

  The whole shebang