More Intel Dual-Core
Apples to Two Apples
Itís almost anti-climactic that the dual-core Pentium D, to be introduced in the second quarter, is simply a monolithic (single die) design with two Prescott cores running in tandem (the projectís name is more commonly referred to as Smithfield). And to that end, the design is nearly what youíd expect from a pair of Xeon DP chips in a workstation.
Each core on the die has its own execution resource pool, its own 1MB L2 cache repository, and its own bus interface. Unfortunately, as with Intelís Xeon family, both cores are forced to share available front side bus bandwidth and at least for now, dual-core chips will top out on 800 MHz buses. As a result, the limitations of Intelís current bus technology versus competing designs remain intact.
Many of the technologies recently exposed on the Pentium 4 are also part of the Pentium D. EM64T, for example, is seemingly now a staple in Intelís desktop arsenal. The Execute Disable bit, compatible with Windows XP Service Pack 2, is also present and accounted for.
Smithfield (90nm) is one piece of silicon with two cores
Presler (65nm) will be two pieces of silicon, also two cores
Moving forward, Intel plans to leverage manufacturing advances with a 65nm dual-core processor codenamed Presler. Rather than employ one die with two cores, Presler leverage two cores on two separate dies co-existing on a single package. Splitting the two die apart shouldnít make a perceptible performance difference, but we can only assume it simplifies manufacturing somewhat, as the complexity of a single die is halved, improving yields. Presler isnít expected until the first half of 2006, but it, like Smithfield will continue communicating over a shared MCH bus.
Around the same time Intel says it will launch Paxville, the Xeon MP dual-core equivalent on a 90nm manufacturing process, and Dempsey, a 65nm Xeon DP dual-core chip at 65nm. The two server/workstation designs will interact with brand new chipsets, each sporting a pair of front side buses to counteract Intelís shared topology.