New North Bridge
Traditional North Bridge/South Bridge architecture
When AMD integrated the memory controller on the Athlon 64 processor’s core itself, a huge amount of real estate was freed up within the chipset. NVIDIA used this space to integrate all the functions found in the nForce3/nForce4 chipsets into a single chip. By moving to a single chip design, latency is reduced. Single-chip designs also free up more space on the board for motherboard manufacturers.
One key downside for the single-chip architecture though is the rapidly changing pace of the hardware industry. If a chipset manufacturer wishes to integrate a new storage technology for instance, the manufacturer has to redesign the entire chipset. Under the more traditional North Bridge/South Bridge configuration, the manufacturer would only have to redesign the South Bridge. This helps the chipset manufacturer integrate new technologies into existing chipsets more easily. The multiple follow-up versions to the original nForce2 chipset is a perfect example of this.
Since the Pentium 4 CPU doesn’t feature an integrated memory controller, the onus is once again on NVIDIA to produce a dedicated high-performance memory controller for their nForce4 SLI Intel Edition chipset.
The nForce4 SLI SPP
nForce4 SLI Intel Edition SPP
With dedicated chips for the North Bridge and South Bridge, NVIDIA has dusted off an old acronym from the nForce/nForce2 days for the North Bridge of the chipset, the SPP, otherwise known as the system platform processor.
The key component of the SPP is the memory controller. Like NVIDIA’s TwinBank memory controller for nForce/nForce2, the NF4 SLI Intel Edition SPP is a 128-bit dual-channel memory controller, consisting of two 64-bit memory controllers. The SPP’s memory controller only supports DDR2 memory. NVIDIA chose not to support DDR memory because “supporting legacy DDR memory required multiple design compromises that would affect system performance”.
DDR2 memory types supported is quite robust. Not only does the SPP support the same 400MHz and 533MHz memory modules as the 925XE chipset, it also one ups 925XE by supporting 667MHz DDR2 memory speeds. At 667MHz, these modules are capable of supplying the processor with up to 10.6GB/sec of peak memory bandwidth, 2.0GB/sec more than DDR2-533, making it more than capable of keeping the latest 3.46GHz and 3.73GHz Pentium 4 Extreme Edition processors fed with data.
To achieve low latencies at high clock speeds, NVIDIA has added a number of enhancements to the SPP. For instance, in the NF4 SLI Intel Edition SPP, NVIDIA provides a dedicated address and command bus for each DIMM, rather than sharing busses across multiple DIMMs. NVIDIA claims that this allows them to hit high clock speeds with 1T address timing, reducing memory latency and thus improving performance.
QuickSync and DASP at the heart of the memory controller
Dedicated address and command bus per DIMM
Third generation DASP
First introduced in NVIDIA’s original nForce chipset, the Dynamic Adaptive Speculative Pre-Processor (DASP) acts as a data prefetch unit for the nForce4 SPP itself. If you’re not familiar with data prefetching, the concept is simple: the DASP intelligently looks for regular access patterns in memory access, predicts which data will be necessary next, and fetches and places that data inside its cache before it's actually needed. Once the CPU requests the data, it is available for the processor immediately, reducing system latency dramatically.
For nForce4 SLI’s SPP, NVIDIA has overhauled the data prefetcher for use with Intel CPUs, specifically keeping improvements in CPU prefetcher design in mind.