The Cache

Why me?!?

The new Celeron has been described as a "crippled" Coppermine Pentium 3 processor, and we'd have to agree. Intel has to maintain different market segments. The Celeron is targeted for the low-end market, and Intel can't have its low-end chip performing as well as its mid-to-high-end Pentium 3 processor.

Our friends in Santa Clara basically whipped out the crowbar, gave the P3 Coppermine a couple good whacks that Tonya Harding would be proud of, and then introduced the new FC-PGA Celeron. Like the P3, the new Celerons feature SSE support along with a smaller manufacturing process and faster clock speeds. Unfortunately, most of Intel's crippling blows landed in the L2 cache area.

Smaller and slower cache

The first difference you notice between the Coppermine P3 and the new Celeron is the Celeron's smaller cache. The Coppermine P3 has 256KB of L2 cache, but the Celeron only has 128KB. Having less cache on the Celeron isn't new. The original Celeron had no L2 cache, and later Celerons only had 128KB of L2 cache.

Of course, everything's relative when you're comparing performance. Back in the day, a Celeron 300A overclocked to 450MHz could hold its own and even beat the then top of the line P2-450. Things have changed since then. Yes, the old Mendocino based Celeron was able to hang in there with a processor that had four times the cache, but you have to remember that the Celeron had on-die cache while the P2 only had discrete, off-chip cache.

Today's Celeron has to compete against the P3 Coppermine, a chip with twice as much on-die cache. The Celeron no longer has a speed advantage to make up for its smaller cache. Too add insult to injury, the Celeron also has a higher L2 cache latency.

Update:
We sent off an e-mail to Intel asking about the differences between the P3 and the new Celeron. Here's what Intel's George Alfs had to say:

The 0.18 micron Pentium(R) III processor has 256KB of eight-way set associative on die L2 cache. The latest Celeron processor has 128K of four-way set associative on die L2 cache. Both processors have the same clock counts as far as latency. We don't disclose how many clocks, but they are the same for both products.

Well, that eliminates the latency issue. Let's move on.

Less associative cache

AnandTech recently pointed out that the Celeron has a 4-way set associative cache. The P3 Coppermine has an 8-way set associative cache. Increasing the degree of associativity usually decreases the miss rate, but increases the hit time. Since we don't know the performance penalties for a miss or the average hit times for either chip, we can't really say which way is better.

Let's take a look at how the Celeron performs against a Pentium 3 when both processors are set at the same clock and bus speed.